1. Field
The present disclosure generally relates to lock loop circuits, and more particularly, to lock loop circuits having a reduced time required to lock frequency and phase.
2. Related Art
Lock loop circuits such as phase lock loop (PLL) circuits provide an output signal having a frequency and phase that is locked to a reference signal. More specifically, PLL circuits use feedback to adjust the output signal so that the frequency and phase of the output signal match the reference signal.
As known in the art, PLL circuits are used in many applications such as radio, telecommunications, computers, and other suitable applications. For example, the circuits can be used to, among other things, generate stable frequencies, recover signals from noisy communication signals, and provide clock timing for applications requiring a stable clock.
Some mobile devices include power management systems that disable phase lock loop circuits when not in use in order to reduce power consumption and increase battery life. Since PLL circuits are used for timing in many devices, it is desirable for the circuit to quickly lock frequency and phase when the power management system re-enables the circuit.
As shown in FIG. 1, a typical PLL circuit 100 includes an error detector 102, a loop filter 104, a voltage controlled oscillator (VCO) 106, and a feedback divider 108. The loop filter 104 includes a resistor 110, a first capacitor 112, and a second capacitor 114. The resistor 110 is operatively coupled to the error detector 102 and the VCO 106 at one end and the first capacitor 112 at the other end. The first capacitor 112 is operatively coupled to the resistor 110 at one end and to ground 116 at the other end. The second capacitor 114 is operatively coupled to the error detector 102 and the VCO 106 at one end and ground 116 at the other end.
During operation, the error detector 102 provides an unfiltered VCO control voltage 116 in response to a reference frequency signal 118 and feedback frequency signal 120. More specifically, the error detector 102 adjusts the unfiltered VCO control voltage 116 to reduce a frequency and phase difference between the reference frequency signal 118 and the feedback frequency signal 120.
The loop filter 104 filters the unfiltered VCO control voltage 116 to remove any imperfections and provides a VCO control voltage 122 (e.g., a steering voltage) based thereon. The VCO 106 provides an output frequency signal 124 in response to the VCO control voltage 122. The feedback divider 108 provides the feedback frequency signal 120 in response to the output frequency signal 124.
In some embodiments, the PLL circuit 100 includes a loop precharger 126 to reduce time required for the PLL circuit 100 to lock frequency and phase. In response to a PLL enable signal 128, the loop precharger 108 provides the unfiltered VCO control voltage 116, which precharges the first and second capacitors 112, 114. In this manner, the VCO control voltage signal 122 is adjusted to a desired value faster than PLL circuits without the loop precharger 126.
Although the loop precharger 126 reduces time for the PLL circuit 100 to lock the frequency and phase of the output frequency signal 124, it is desirable to further reduce the time required to lock the frequency and phase.
In addition, the first and second capacitors 112, 114 are known to leak current to ground, which increases power consumption and noise of the PLL circuit 100. Therefore, it desirable to provide a PLL circuit having a loop filter with reduced current leakage to ground.